[tor-dev] Summer 2017 Internship to Create a Bridge Bandwidth Scanner
isis agora lovecruft
isis at torproject.org
Thu Jun 15 23:08:03 UTC 2017
Damian Johnson transcribed 2.0K bytes:
> On Thu, Jun 15, 2017 at 2:07 PM, teor <teor2345 at gmail.com> wrote:
> >> On 16 Jun 2017, at 03:49, isis agora lovecruft <isis at torproject.org> wrote:
> >> Hello all!
> >> I have made a brief post on our blog to announce an exciting intership
> >> opportunity we have available!
> >> https://blog.torproject.org/blog/summer-2017-internship-create-bridge-bandwidth-scanner
> > stem also does circuit construction via the control port, so the
> > intern can avoid doing anything twisted... if they want.
> > There's even TorCtl, but it's old and unmaintained.
> Hi Isis. For what it's worth if it turns out to be based on Stem I'd
> be delighted to help mentor and/or do code reviews.
> Also, I agree with Tim. The present wording makes it sound like
> txtorcon is the only game in town when it comes to custom circuit
> construction. Lots of options, and even if they don't do it in python
> it's not hard. :)
Sorry, in my nearsightedness, having only ever had used Stem for parsing, I
had not realised that enough of the control protocol was implemented in Stem
to do this without using txtorcon! Please feel free to reword the posting (or
suggest a change) that you think would more accurately reflect this.
Also, I would be delighted to co-mentor with you (and also meejah, if the
intern decides to go the txtorcon route), that sounds great!
♥Ⓐ isis agora lovecruft
Current Keys: https://fyb.patternsinthevoid.net/isis.txt
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