[tor-bugs] #2114 [Vidalia]: Vidalia network map should distinguish circuit types (was: The network map should distinguish between general and internal circuits)

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#2114: Vidalia network map should distinguish circuit types
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 Reporter:  arma     |       Owner:  chiiph
     Type:  defect   |      Status:  new   
 Priority:  normal   |   Milestone:        
Component:  Vidalia  |     Version:        
 Keywords:           |      Parent:        
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Description changed by arma:

Old description:

> Some users get confused by the fact that only general purpose circuits
> end with exit nodes, leading them to believe Tor is ignoring their
> ExitNodes and StrictExitNodes config options; see e.g.
> https://trac.torproject.org/projects/tor/ticket/601
>
> Vidalia should do something to distinguish between the two circuit
> purposes to make users less confused.
>
> Originally from https://trac.vidalia-project.net/ticket/335

New description:

 In Vidalia's network map we show circuits that Tor is building. That's
 great, but there are cases where it confuses users. In particular, some
 Tor circuits are 1-hop (for fetching directory information but also using
 a layer of encryption), and some are internal (for everything other than
 attaching exit streams). Many users are concerned by the one-hop circuits
 they see (thinking that Tor is planning to use them for exit streams), and
 a smaller but still significant number of users set ExcludeExitNodes and
 then freak out when Tor uses that node as the last hop in an internal
 (non-exit) circuit. I think both cases would be partially resolved by
 having Vidalia present the circuit list more clearly.

 How would we do this? One option would be a "type" column in the circuit
 listing, where we describe each circuit as "directory", "exit", or
 "internal". Another option would be to have separate rows in the circuit
 listing: put all the exit circuits at the top under the heading "exit
 circuits", then "internal circuits" and the list of internal circuits,
 then finally all the 1-hop directory circuits with their own heading. I
 like option 2 slightly better. I wonder if there are still better
 approaches?

 Vidalia can learn the circuit purpose via the controlport, from the (alas
 undocumented) "PURPOSE=" argument in circuit status. But I think we don't
 export other flags, like "build_state->onehop_tunnel". We should first
 change Tor so it exports these flags in a more usable way.

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Ticket URL: <https://trac.torproject.org/projects/tor/ticket/2114#comment:2>
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